Upconverter Design and Manufacturing, Continued
Over the course of the semester, the upconverter board was successfully designed and manufactured. This process followed the design philosophy outlined in the interim report and resulted in the production of a board that was functional and capable of producing the required signal outputs.
The resulting upconverter board was a 4 layered, hybrid stackup, which made use of both high performance RO4003C laminate and traditional FR4 to balance between cost and performance. In addition to the previous considerations (ie. RF performance, Signal Integrity, Cost), certain design features were also included to enhance board performance. Thermal Vias were included under components expected to produce high amounts of heat, such as the HPA regulator and the PLL IC. These thermal vias are electrically connected to the Ground plane, and also filled with conductive copper paste - which allows them to conduct heat generated by the IC to the ground plane thereby maintaining the IC at an acceptable temperature This avoids the need for a separate heat sink. Various test points were also provided to facilitate power debugging.
Additionally, a solder jumper was included to allow switching between various diagnostic modes. On ground, the solder bridge would be set to position 1, which allows quick and easy debugging by allowing the PLL IC to turn the LED indicators on and off to indicate PLL lock status. Before flight, the solder bridge would be set to position 3, to allow the payload computer to access the PLL status via SPI readback - this information can then be transmitted back to earth using the TT\&C link, which will help with diagnostics should there be an issue with the upconverter.
This board was ultimately manufactured by PCBWay, due to their capacity for advanced PCB manufacturing, and then assembled locally at Interhorizon using parts that were consigned to the assembly house. This arrangement was due to the prior working relationship with Interhorizon, and also allowed us greater control of the parts that were used.
IF Input Signal Emulation
One key constraint at the current stage of the project was the lack of access to the actual Gomspace Link SX SDR that would be used on the actual satellite, due to contracting and procurement delays at the programmatic level. This was critical as estimating the actual signal output performance had to be done for the correct input IF signal levels. Therefore, the source IF signal had to be estimated and then emulated using available hardware. This took some investigation as the IF signal from the Link SX product was not meant to be directly accessed, and would normally be used in conjunction with the supplied S and X band antennas. IF signal power therefore was not directly provided in the datasheet for the Link SX.
After some investigation, it was found that the Link SX was designed on Gomspace Nanocom TR600 SDR module. More information was available for this module, and it was found that the output of the TR600 could occur at 4 different power levels, measured in their level of attenuation (0 dB, 10 dB, 20 dB, and 30 dB). At a 0 dB attenuation, the corresponding power level was 6 dBm. In general, the upconversion chain was designed to work with a nominal IF input of -9 dBm - therefore, the power levels most appropriate for the test would be the 10 dB and 20 dB attenuation levels (-4 dBm, -14 dBm)
To produce the IF signal, a B205 Mini SDR was used, which could emulate the 1150 MHz DVBS2 IF signal produced by the Link SX. The software used to generate the DVBS2 signal was SDR angel, and allowed configuring the internal gain of the SDR up to 89 dB. A sample 2MHz DVBS2 signal was generated and the power was measured at different internal gain settings of the B205 Mini.
Baseline measurements on the B205 suggested that the output power was too weak - achieving only -6.3 dBm at maximum internal gain. To address this, a Low noise preamplifier was installed on the IF chain, and the gain settings for 6 dBm, -4 dBm, and -14 dBm were noted down. The preamplifier (PMA3-14LN+) gave about 22.6 dB of gain, allowing the operation of the IF generating SDR well within the linear range.
After some testing, an internal gain setting of 68 dB was found to give a roughly -4 dBm output, corresponding Over the course of testing, this would vary slightly due to cable losses and differences in gain caused by temperature, but is expected to have negligible impact on overall link performance. Testing was then conducted at each of these 3 settings to characterize the RF Chain’s performance. Results will be discussed for the 10 dB attenuation (-4 dBm) case, as that will likely be representative of the configuration used on the flight model. Other results will be made available in Appendices () through ().
| SDR Angel - Internal Gain Setting | Measured Output Power at Preamplifier |
|---|---|
| 78 dB | 5.66 dBm (6 dBm, 0 dB Attenuation Setting) |
| 68 dB | -3.94 dBm (-4 dBm, 10 dB Attenuation Setting) |
| 58 dB | -13.9 dBm (-14 dBm, 20 dB Attenuation Setting) |
Space Segment RF Chain Testing and Characterization Plan
A series of tests were conducted, to identify the performance characteristics of the upconverter and the broader spacebourne RF chain. Of primary concern was the ability of the spaceborne segment to downlink at the correct power level, within an acceptable level of signal degradation for direct to VSAT transmission and data recovery.
The series of tests that were conducted:
- SDR output power test (Select Settings to match TR600 Radio Module, see preceding section)
- Filter Power Output Test
- Mixer + Filter Loss estimation
- LNA Output Power Test
- LNA Gain Estimation
- HPA Power Output Test
- HPA Gain Calculation
- Spurious Emission, HPA Output
For the purposes of assessing whether the level of signal degradation was acceptable, an end to end test was conducted where data was transmitted over the air at designed frequency and power levels, before being recovered.
RF Power Characterization
Upon powering the upconverter and writing the SPI bitstream to initialize the PLL IC, it was first necessary to verify that the PLL was producing the correct LO signal. The Spectrum Analyzer was connected to the Coupled LO output to verify that the signal was being produced correctly, and a power measurement was performed. This confirmed that the LO was producing the intended 12.8 GHz LO signal, with an power level of approximately -7 dBm after accounting for the 20 dB attenuation of the coupler. Ordinarily, LO drive power would have to be carefully considered (roughly 4 to 7 dBm above IF power) to avoid output compression, and also because the Mixer requires a sufficiently strong LO signal to drive its internal circuitry. This requirement is not particularly critical in the present case as the mixer chosen has an internal buffer, and will boost the LO signal to a sufficiently strong level to drive the mixer and avoid compression issues.
Next, the power output of the upconverter was measured. This is the same input signal that will enter the high powered amplifier (HPA), and has to be sufficiently strong to ensure the desired transmit power (33 dBm) is obtained, but not too strong such that the HPA is driven into saturation. At a - 4 dBm IF input level, this results in a power output of approximately -0.55 dBm. which was very close to the theoretical designed value 0.2 dBm
Finally, to complete the upconverter chain characterization and determine the LNA gain and losses incurred by the filter and mixer, a power reading from the filter output is required which will then allow us to backcalculate the necessary values. At the -4 dBm input level, the estimated output power from the mixer and filter segment was approximately -30 dBm. This was considerably further from the targeted theoretical design value of -22.8 dBm.
With all three values, we may estimate the relevant gain and losses and characterize the components in the upconversion chain:
| Component | Value |
|---|---|
| LO Output Power | -7 dBm |
| Conversion, Filtering Losses | 24 dB |
| Preamplifier Gain | 29.45 dB |
After the upconverter was characterized, the HPA was added into the RF chain and the power output measured. To keep the test setup as close to the actual hardware that will be flown, the
HPA was powered from the HPA supply regulator hosted on the Upconverter Board. This regulator is a buck converter which regulates Raw battery voltage (24V - 32V) to 15V. The power produced by the HPA at -4 dBm input to the upconverter was measured at 31.59 dBm, 1.4 dB lower than the targeted value. This corresponds to approximately 1.44W. Further testing revealed that high temperatures affected the available gain of the amplifier. After 20 minutes of operation, the available signal power had dropped to approximately 29 dBm. While not characterized by the manufacturer, the drop in gain is expected and will be mitigated through the installation of the heatsink. Furthermore, it is unlikely the HPA will be operated for that long due to the requirements of the mission.
Spurious Emission Testing
As a final characterization test, the RF chain had to be characterized for spurious emissions. The primary regulation governing spurious emissions - ie. emissions outside of the necessary bandwidth required for transmission is the International Telecommunication Union’s (ITU) Reference SM.329 (Unwanted emissions in the spurious domain). This defines the various spurious emission power levels allowable for different use cases. In our case, as a space service transmitter, the required attenuation from the transmission line power (ie. the power at which the intended signal is transmitted at) is given by 43 dB + 10 log (P), where P is power in watts. For a transmission power of 2W, this results in an attenuation of 46 dB. The spurious emission power must therefore fall below 46 dB of attenuation, within the 250% range of the necessary bandwidth given a 2 MHz transmission bandwidth.
Thermal Characterization
During the tests conducted, it was observed that the regulator supplying the LNA power supply would occasionally cutout. This was traced to the LDO regulator powering the LNA, and it was determined that excessive heat was being generated by the LDO, triggering its inbuilt thermal protection. While the current and power consumed from the LNA was not high (nominally 68 mA), the high battery voltage and low regulated voltage - a 28V drop - caused much higher powers to be dissipated through the LDO. The recommended footprint in the datasheet was followed, and there were no thermal guidelines available during the design.
Thermal analysis subsequently confirmed that heat related problems was causing the LDO to enter thermal protection mode. Thermal Protection is triggered when the LDO junction temperature reaches 175 deg C, and is released upon falling below 150 deg C. Thermal images indicated (as with the example shown to the right), that peak temperatures around the LDO could easily reach such values. Furthermore, it was observed that thermal protection occurs more commonly when the room temperature is warmer, further supporting this observation. For the purposes of testing, a fan was therefore pointed at the upconverter during extended operations.
It was also noted that both the HPA supply regulator and the PLL were operating within their temperature limits, confirming the effectiveness of the thermal via cooling solution implemented for both ICs.
Future Improvement and Works
The work undertaken for the Ku Band Downlink system occurs as part of broader work on the Galassia 5 mission. Work on the second version of the board had therefore progressed under the broader program as characterization work was being done on the current generation upconverter design. The lessons learnt during the characterization tests have been passed on to the junior batches working on version 2 of the board and are currently informing design choices and priorities being made.
Reworking of RF Traces to improve cross trace isolation and noise
During the design of the board, the primary consideration was expediting the design for initial characterization tests. Some features, such as IC couplers, were only added in during the late stages of the design. As a result, the layout was not fully optimized. In version two of the board, a mandate was given to: 
- Shorten all RF traces to the minimum necessary (constrained by component size and clearances on connectors)
- Reduce meandering of the traces
- Increase separation of traces of different signals
These help to reduce unnecessary losses and coupling between the traces. In particular, implementing point 2 also opens up the opportunity for the installation of isolation walls - conductive copper barriers that prevent RF from being radiated out from the trace lines and crossing into different traces. The isolation walls can be fashioned out of copper foil or thin copper plates, which will then be electrically connected to ground.
Installation of Variable Pi Attenuator
As all RF components may have manufacturing variations, causing the gain in amplifiers to be higher or lower than expected, it is necessary to account for such variations in the design of the RF chain. The current design takes accounts such variations by allowing the user to configure the IF output power on the Link SX radio to the 0 dBm attenuation setting if so required, therefore increasing the resultant upconverter output power.
However, as the HPA already operates very close to the saturation point, the 0 dBb Attenuation configuration will result in a 10 dB increase in the input power level, causing the HPA to saturate, increasing the power of spurious emissions and resulting in a dirtier signal. Therefore, a pi attenuator will be installed into the IF input chain of the upconverter board, allowing the IF signal to be attenuated to a level between the 0 dB and -10dB attenuation power levels. This attenuator consists of a set of resistors, whose values can be changed accordingly to achieve the correct attenuation level.
Thermal Management for LDO
To reduce thermal power dissipated by the LDO and prevent the thermal protection from kicking in, two measures were taken:
- The input voltage was dropped from Vbatt, to a regulated 5V supply.
- Thermal vias were included to facilitate the conduction of heat from the LDO IC to the ground plane
In particular, the reduction of input voltage from V Batt to 5V would already represent a roughly 6 times decrease in thermal load generated by the LDO. The thermal vias are provided as a contingency should other supply voltages become necessary in the future.